Built-in system and method for testing integrated circuit timing parameters

ABSTRACT

A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the memory device responsive to respective clock signals. The clock signal are generated by a test system oscillator and coupled through a clock tree of the memory device. The test system further includes a selector that sequentially selects each of the test signals applied to the data bus terminals and applies the selected test signal to a multi-phase generator. The multi-phase generator delays the selected signal by different time to generate a set of delayed signals. The phases of the delayed signals are compared to the test signal applied to the data strobe terminal to determine the delay of the compared signals relative to each other, thereby determining the timing parameter.

TECHNICAL FIELD

This invention relates to integrated circuit devices such as memorydevices, and, more particularly, to a method and system included in anintegrated circuit for testing timing parameters in the integratedcircuit device.

BACKGROUND OF THE INVENTION

During the fabrication of integrated circuits such as memory devices, itis conventional to test such integrated circuits at several stagesduring the fabrication process. For example, the integrated circuits arenormally connected to a tester with a probe card when the integratedcircuits are still in wafer form. In a final test occurring after theintegrated circuits have been diced from the wafer and packaged, theintegrated circuits are placed into sockets on a load board. The loadboard is then placed on a test head, typically by a robotic handler. Thetest head makes electrical contact with conductors on the load boardthat are connected to the integrated circuits. The test head isconnected through a cable to a high-speed tester so that the tester canapply signals to and receive signals from the integrated circuits.

One type of tests typically performed on integrated circuits such asmemory devices are tests of the timing margins of the integratedcircuits. For example, one memory device timing parameter that isnormally tested is the skew of a data strobe signals DQS with respect tolast read data signal DQ to become valid, which is abbreviated ast_(DQSQ). Another memory device timing parameter that is normally testedis the DQ-DQS hold time, abbreviated as t_(QH), which is the skew of theDQS signal with respect to the first DQ signal to become invalid. Insynchronous memory devices, read data signals DQ are output from thememory devices in synchronism with a data strobe signal DQS. Withreference to FIG. 1, the data strobe signal DQS transitions active attime to, and the read data signals DQ then become valid. The maximumtime needed for the last of the read data signals DQ to become validafter the transition of DQS at t₀, i.e., t_(DQSQ), is normally specifiedfor a memory device. The timing parameter t_(DQSQ) thus represents themaximum acceptable skew between the last of the read data signals DQthat becomes valid and the data strobe signal DQS. Similarly, theminimum time that the earliest of the read data signals DQ becomesinvalid after the transition of DQS at t₀, i.e., t_(QH), is alsonormally specified for a memory device.

The time between t_(DQSQ) and t_(QH) is the data valid period. Thelength of the data valid period may be excessively reduced by anyincrease in the DQS-DQ skew beyond the specified maximum t_(DQSQ) or anydecrease of the DQ-DQS hold time from the specified t_(QH). As thelength of the data hold period gets smaller, it becomes more difficultfor the memory device to position transitions of the DQS signal at thestart of the data valid period. It is therefore important to determinethe data set-up and data hold times of a memory device being tested toensure that a sufficient data valid period can be achieved.

The above-described testing environment works well in many applicationsto test the timing parameters of integrated circuits such as memorydevices. However, the testing environment is not without its limitationsand disadvantages. For example, it is very difficult to test varioustiming characteristics of the integrated circuits, particularly at thehigh operating speeds for which such integrated circuits are designed.This difficulty in testing timing characteristics results primarily fromthe propagation delays in the cable coupling the tester to the testhead. The cables that are typically used in such testing environmentsare often fairly long, thus making the delays of signals coupled to andfrom the integrated circuits correspondingly long and often difficult topredict.

Another problem with the above-described testing environment is that itmay not accurately simulate the conditions in which the integratedcircuits will actually be used. In particular, the integrated circuits,and particularly the timing parameters of integrated circuits, are notgenerally tested during use in an actual operating environment and aftera substantial period has lapsed. Therefore, even if the timingparameters of the integrated circuit were within specification when theintegrated circuit was shipped from a fabrication facility, there can beno assurance that the timing parameters are within a specified rangeduring use, particularly after a substantial period of time. Also, it isdifficult to measure a skew between two output ports as opposed tomeasuring a skew between an input port and an output port.

There is therefore a need for a testing system and method that can beeasily fabricated in an integrated circuit to allow the timingparameters of an integrated circuit to be accurately tested duringactual use of the integrated circuit.

SUMMARY OF THE INVENTION

A test system and method for determining the relative timing betweenfirst and second digital signals includes a multi-phase signal generatorthat delays the first digital signal by different delay times togenerate a plurality of delayed signals. The delayed signals arereceived by respective phase detectors each of which also receive thesecond digital signal. Each of the phase detectors generates an outputsignal having a logic level corresponding to the logic level of one ofthe received signals at a predetermined transition of the other of thereceived signals. The output signals are examined to determine theapproximate timing of the first digital signal relative to the seconddigital signal. The test system and method can be used in a memorydevice to determine a timing parameter by determining the relativetiming of signals applied to data bus terminals and a data strobeterminal responsive to respective clock signals coupled through a clocktree of the memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a timing diagram showing a specific relationship between adata signal and a data strobe signal corresponding to a conventionalmemory device timing parameter.

FIG. 2 is a block diagram of a memory device testing system fordetermining a timing parameter of a memory device.

FIG. 3 is a timing diagram showing timing relationships between a datastrobe signal and several different phases of a data signal.

FIG. 4 is a block diagram of one example of a memory device using atiming parameter testing system according to one example of theinvention.

FIG. 5 is a block diagram of a computer system containing the memorydevice of FIG. 4.

DETAILED DESCRIPTION

A built-in self-test system 100 according to one example of theinvention is shown in FIG. 2. The self-test system 100 is preferablyfabricated on the same substrate as a memory device (not shown) beingtested, although other configurations may also be used. The system 100includes a ring oscillator 102 that generates a periodic clock signalthat is used during testing. During normal operation, a clock signal isgenerated by a delay-lock loop 106 responsive to an external clocksignal applied to an external terminal pad 108 and coupled through adriver 110. The advantage of using an internal oscillator is that it maybe possible to make the frequency of the clock signal higher than thefrequency of an externally applied clock signal. A multiplexer 114responds to a t_(DQSQ) test signal to select as an output clock signalthe output of the delay-lock loop 106 during normal operation and theoutput of the ring oscillator 102 during memory device testing. The ringoscillator 102 also outputs an internal clock int_clk signal, which isused by other circuitry in the memory device being tested.

The clock signal from the multiplexer 114 is coupled through a clocktree 118, which distributes the clock signal to a plurality of signaldrivers 120 a-h and 122 a,b. In the example shown in FIG. 2, the drivers120 a-h are provided to output one byte of data, and the drivers 122 a,bare provided to output complementary data strobe signals DQS and DQSB.The logic levels of the signals output by the drivers 120, 122 areprovided by a pattern generating counter 130, which is clocked by theint_clk signal. The drivers 120, 122 output respective logic levels torespective externally accessible data terminals 126 a-h and data strobeterminals 128 a,b, respectively, responsive to the received clocksignals. Therefore, the drivers 120 a-h apply incrementing patterns ofdata to the respective data terminals 126 a-h in phase with the DQS andDQS terminals applied to the terminals 128. The signals applied to theterminals 126 by the drivers 120 during testing mimic read data signalsthat the drivers 120 a-h apply to the terminals 126 during normaloperation. Similarly, the signals applied to the terminals 128 by thedrivers 122 during testing mimic data strobe signals that the drivers122 apply to the terminals 128 during normal operation. However, in bothnormal operation and during testing, the drivers 120, 122 output signalresponsive to clock signals coupled through the same clock tree 118.

The data and data strobe signals applied to the terminals 126, 128,respectively, are coupled to a DQ and DQS selector 140. The selector 140selects one of the data signals applied to the data terminals 126 a-hand one of the data strobe signals applied to the DQS terminals 128 a,bresponsive to a select signal, which is generated by a shift register144. The shift register 144 sequentially selects the data signals fromeach of the data terminals 126 a-h and the data strobe signal from oneof the DQS terminals 128 responsive to the int_clk signal.

The data signal selected by the selector 140 is applied to a firstmulti-phase signal generator circuit 150, and the data strobe selectedby the selector 140 is applied to a second multi-phase signal generatorcircuit 154. In the example shown in FIG. 2, each of the multi-phasesignal generator circuits 150, 154 includes six phase mixers 160 a-f,which receive the selected data or data strobe signal and a delayedversion of such signal through a delay unit 164. The phase mixers 160a-f generate respective delayed signals on a 6-bit bus. The delay of thedelayed signals vary between substantially zero delay and the delayprovided by the delay unit 164. If the delay unit 164 delays thereceived signal by t_(D), the delayed signals from the respective phasemixers 160 a-f will have respective delays of 0, 0.2 t_(D), 0.4 t_(D),0.6 t_(D), 0.8 t_(D) and t_(D).

The six delayed signals from the first multi-phase signal generatorcircuit 150 and the six delayed signals from the second multi-phasesignal generator circuit 154 are applied to phase detectors 170. Thephase detectors 170 compare the timing of transitions of each of thedelayed data signals from the first multi-phase signal generator circuit150 with corresponding transitions of the zero delay output from thephase mixer 160 a in the second multi-phase signal generator circuit154. The phase detectors 170 also compare the timing of transitions ofeach of the delayed data strobe signals from the second multi-phasesignal generator circuit 154 with corresponding transitions of the zerodelay output from the phase mixer 160 a in the first multi-phase signalgenerator circuit 150. Based on these comparisons, the timing of thedata signal selected by the selector 140 relative to the timing of thedata strobe signal selected by the selector 140 can be determined.

The manner in which the signal generator circuits 150, 154 and the phasedetectors 170 can determine the timing of the data signal relative tothe timing of the data strobe signal will now be explained with respectto the signals shown in FIG. 3. The first six signals shown in FIG. 3are the data signals DQ output from each of the phase mixers 160 a-fwith delays corresponding to the respective K values. The final signalshown in FIG. 3 is the data strobe signal DQS selected by the selector140, which is generated by the phase mixer 160 a in the secondmulti-phase signal generator circuit 154. As explained in greater detailbelow, the phase detectors 170 used in the system 100 of FIG. 2 mayoutput a logic level corresponding to the logic level of the DQS signalat the rising edge of each of the DQ signals. Therefore, the phasedetectors 170 for the K=0, K=0.2 and K=0.4 phases of the DQ signal willoutput a “0,” and the phase detectors 170 for the K=0.6, K=0.8 and K=1phases of the DQ signal will output a “1.” The bits from all of thephase detectors 170 are thus “000111.” These bits can be used todetermine the time that the data signal DQ leads the data strobe signalDQS according to the following table:

TABLE 1 BIT PATTERN DQ Leads DQS By 0 0 0 0 0 0 >t_(D) 0 0 0 0 0 10.8t_(D)-t_(D) 0 0 0 0 1 1 0.6t_(D)-0.8t_(D) 0 0 0 1 1 10.4t_(D)-0.6t_(D) 0 0 1 1 1 1 0.2t_(D)-0.4t_(D) 0 1 1 1 1 1 0-0.2t_(D) 11 1 1 1 1 DQS Leads DQA similar table obtained from the phase detectors 170 corresponding tothe logic level of the DQ signal at the rising edge of each of the DQSsignals from the phase mixer 160 a-f in the second multi-phase signalgenerator 154 provides an indication of the degree to which the DQsignal lags the DQS signal. In this case, the DQ signal is generated bythe phase mixer 160 a in the first multi-phase signal generator 150 forK=0.

The bit patterns corresponding to these comparisons are applied tolatches 174, which latch the bit patterns. Signals corresponding to thelatched bit patterns are then output from the self-test system 100.These signals from the latches 174 may be output from the memory devicecontaining the self-test system 100 so that an external device candetermine the value of the timing parameter t_(DQSQ).

In operation, all possible patterns of signals corresponding torespective counts of the pattern generating counter are applied to thedata and data strobe terminals responsive to the clock signal from thering oscillator. As each pattern is applied to the data and data strobeterminals, a first of the data terminals and one of the data strobeterminals are coupled to the first and second multi-phase signalgenerator circuits 150, 154, respectively, by the selector. The signalsfrom the signal generator circuits 150, 154 are compared as describedbelow, and the resulting comparison signals latched. More specifically,the relative timing between the rising edge of the selected data signaland the rising and falling edges of the DQS signal is first determined.Next, the relative timing between the falling edge of the selected datasignal and the rising and falling edges of the DQS signal is determined.The same process is repeated with the selector 140 coupling the otherdata strobe signal DQSB to the signal generator 154 so that the system100 can determine the timing of the rising edge of the selected datasignal relative to the rising and falling edges of the DQSB signal.Finally, the timing of the falling edge of the selected data signal iscompared in the same manner to the rising and falling edges of the DQSBsignal. Based on these signals, the worst-case propagation delay throughthe drivers 120 a, 122 a and clock tree 140 can be determined for thepatterns of data signals.

The selector 140 subsequently couples each of the remaining dataterminals 126 and the DQS terminals 128 to the signal generator circuits150, 154 to determine the timing parameter t_(DQSQ) for all of the dataterminals. The worst case value for t_(DQSQ) can be determined andspecified as the t_(DQSQ) parameter for the memory device.

Although the bit pattern from the latches 174 may be output from amemory device after each test, the latches 174 are preferably all resetto “1” prior to starting a test and are not reset until after the testhas been completed. During the test, an increasing number of latches 174are set to “0” depending upon the degree to which each data signal beingtested lags or leads the data strobe signal being tested. After thecompletion of a test, the number of latches 174 that have been set to“0” will correspond to the worst case skew of the data signals relativeto the data strobe signals. The bit pattern 174 can then be output fromthe memory device at the conclusion of the test, and it will correspondto the timing parameter t_(DQSQ).

FIG. 4 is a block diagram of a conventional synchronous dynamic randomaccess memory (“SDRAM”) 270 that uses a built-in self test systemaccording to one example of the invention. However, it will beunderstood that test systems according to various examples of theinvention can also be used in other types of DRAMs as well as in othertypes of memory devices. The operation of the SDRAM 270 is controlled bya command decoder 274 responsive to high level command signals receivedon a control bus 276. These high level command signals, which aretypically generated by a memory controller (not shown in FIG. 4), are aclock enable signal CKE*, a clock signal CLK, a chip select signal CS*,a write enable signal WE*, a row address strobe signal RAS*, and acolumn address strobe signal CAS*, in which the “*” designates thesignal as active low. The command decoder 274 includes the driver 110receiving the external clock signal CLK, which is selectively enabled bythe clock enable signal CKE*. As explained above, the output of thedriver 110 is applied to a delay lock loop 106, which output a clocksignal to the multiplexer 114. As also explained above, the multiplexer114 also receives the clock signal from the ring oscillator 102, and itis controlled by the t_(DQSQ) test signal. In the SDRAM 270 shown inFIG. 4, the t_(DQSQ) test signal is generated by a mode register 275included in the command decoder 274. Regardless of whether the DLL 106or the oscillator 102 generates the clock signal, the clock signal isdistributed through the clock tree 118 as clock signals C₀, C₁ . . . C₉to circuitry that will be described below.

The command decoder 274 also generates a sequence of command signalsresponsive to the high level command signals to carry out the function(e.g., a read or a write) designated by each of the high level commandsignals. These command signals, and the manner in which they accomplishtheir respective functions, are conventional. Therefore, in the interestof brevity, a further explanation of these control signals will beomitted.

The SDRAM 270 includes an address register 282 that receives either arow address or a column address on an address bus 284. The address bus284 is generally coupled to a memory controller (not shown in FIG. 9).Typically, a row address is initially received by the address register282 and applied to a row address multiplexer 288. The row addressmultiplexer 288 couples the row address to a number of componentsassociated with either of two memory arrays 290, 292 depending upon thestate of a bank address bit forming part of the row address. Associatedwith each of the memory arrays 290, 292 is a respective row addresslatch 296, which stores the row address, and a row decoder 298, whichdecodes the row address and applies corresponding signals to one of thearrays 290 or 292.

The row address multiplexer 288 also couples row addresses to the rowaddress latches 296 for the purpose of refreshing the memory cells inthe arrays 290, 292. The row addresses are generated for refreshpurposes by a refresh counter 300, which is controlled by a refreshcontroller 302. The refresh controller 302 is, in turn, controlled bythe command decoder 274.

After the row address has been applied to the address register 282 andstored in one of the row address latches 296, a column address isapplied to the address register 282. The address register 282 couplesthe column address to a column address latch 310. Depending on theoperating mode of the SDRAM 270, the column address is either coupledthrough a burst counter 312 to a column address buffer 314, or to theburst counter 312 which applies a sequence of column addresses to thecolumn address buffer 314 starting at the column address output by theaddress register 282. In either case, the column address buffer 314applies a column address to a column decoder 318, which applies variouscolumn signals to corresponding sense amplifiers and associated columncircuitry 320, 322 for one of the respective arrays 290, 292.

Data to be read from one of the arrays 290, 292 is coupled to the columncircuitry 320, 322 for one of the arrays 290, 292, respectively. Thedata is then coupled to a data output register 326. The data outputregister 326 couples the read data to the data bus terminals 126responsive to the clock signals C₀, C₁ . . . C₇ that are coupled throughthe clock tree 118. In the t_(DQSQ) test mode, the data signals arecoupled to the data output register 326 from the pattern generatingcounter 130, and they are applied to the data bus terminals 126responsive to the clock signals C₀, C₁ . . . C₇ that are coupled throughthe clock tree 118. In a similar manner, the data output register 326applies complementary data strobe signals DQS and DQSB to the datastrobe terminals 128 responsive to the clock signals C₈, C₉.

Data to be written to one of the arrays 290, 292 are coupled from thedata bus terminals 126 through a data input register 330 to the columncircuitry 320, 322 where it is transferred to one of the arrays 290,292, respectively. A mask register 334 may be used to selectively alterthe flow of data into and out of the column circuitry 320, 322, such asby selectively masking data to be read from the arrays 290, 292.

During the t_(DQSQ) test mode, the data signals applied to the data busterminals 126 and the data strobe signals applied to the data strobeterminals 128 are applied to the selector 140, as previously explained.At the conclusion of the t_(DQSQ) test, the latches 174 apply the testresults to the data bus terminals 126 so an external device candetermine the value of the timing parameter t_(DQSQ) for the SDRAM 270.

FIG. 5 shows an embodiment of a computer system 400 that may use theSDRAM 270 or some other memory device that contains a timing parametertest system according to one example of the invention. The computersystem 400 includes a processor 402 for performing various computingfunctions, such as executing specific software to perform specificcalculations or tasks. The processor 402 includes a processor bus 404that normally includes an address bus 406, a control bus 408, and a databus 410. In addition, the computer system 400 includes one or more inputdevices 414, such as a keyboard or a mouse, coupled to the processor 402to allow an operator to interface with the computer system 400.Typically, the computer system 400 also includes one or more outputdevices 416 coupled to the processor 402, such output devices typicallybeing a printer or a video terminal. One or more data storage devices418 are also typically coupled to the processor 402 to store data orretrieve data from external storage media (not shown). Examples oftypical storage devices 418 include hard and floppy disks, tapecassettes, and compact disk read-only memories (CD-ROMs). The processor402 is also typically coupled to a cache memory 426, which is usuallystatic random access memory (“SRAM”) and to the SDRAM 270 through amemory controller 430. The memory controller 430 includes an address buscoupled to the address bus 284 (FIG. 4) to couple row addresses andcolumn addresses to the SDRAM 270, as previously explained. The memorycontroller 430 also includes a control bus that couples command signalsto a control bus 276 (FIG. 4) of the SDRAM 270. The external data bus328 (FIG. 4) of the SDRAM 270 is coupled to the data bus 410 (FIG. 5) ofthe processor 402, either directly or through the memory controller 430.The memory controller 430 applies appropriate command signals to theSDRAM 270 to cause the SDRAM 270 to operate in the t_(DQSQ) modedescribed above.

Although the present invention has been described with reference to thedisclosed embodiments, persons skilled in the art will recognize thatchanges may be made in form and detail without departing from the spiritand scope of the invention. For example, although the test system hasbeen described as being used to determine the timing parameter t_(DQSQ)for memory devices, it may also be used to measure other timingparameters with suitable modifications that will be apparent to oneskilled in the art. Accordingly, the invention is not limited except asby the appended claims.

1. A system for determining the relative timing between first and seconddigital signals, comprising: a multi-phase signal generator receivingthe first digital signal, the multi-phase signal generator comprising adelay circuit receiving the first digital signal and being structured todelay the first digital signal to produce a delayed signal that isdelayed from the first digital signal by a first delay time, themulti-phase signal generator further comprising a plurality of phasemixers receiving the first digital signal and the delayed signal, thephase mixers being structured to generate respective multi-phase signalsthat are delayed by respective percentages of the first delay time; anda plurality of phase detectors each of which is coupled to receive thesecond digital signal and a respective one of the multi-phase signalsfrom the multi-phase signal generator, each of the phase detectors beingstructured to generate an output signal having a logic levelcorresponding to the logic level of one of the second digital signal andthe respective multi-phase signal at a predetermined transition of theother of the second digital signal and the respective multi-phasesignals.
 2. The system of claim 1, further comprising: a secondmulti-phase signal generator receiving the second digital signal, thesecond multi-phase signal generator comprising a delay circuit receivingthe second digital signal and being structured to delay the seconddigital signal to produce a second delayed signal that is delayed fromthe second digital signal by a second delay time, the multi-phase signalgenerator further comprising a plurality of phase mixers receiving thesecond digital signal and the second delayed signal, the phase mixersbeing structured to generate respective second multi-phase signals thatare delayed by respective percentages of the second delay time; and aplurality of second phase detectors each of which is coupled to receivethe first digital signal and a respective one of the second multi-phasesignals from the second multi-phase signal generator, each of the secondphase detectors being structured to generate an output signal having alogic level corresponding to the logic level of one of the first digitalsignal and the respective second multi-phase signal at a predeterminedtransition of the other of the first digital signal and the respectivesecond multi-phase signal.
 3. The system of claim 1, further comprisinga plurality of latches coupled to receive respective output signals fromthe phase detectors, the latches being operable to store the receivedoutput signals. 4-28. (canceled)
 29. A method of determining therelative timing between first and second digital signals, comprising:delaying the first digital signal to produce a plurality of delayedsignals that are delayed from the first digital signal by respectivefirst delay times; generating a plurality of first output signals eachof which has a logic level corresponding to the logic level of one ofthe second digital signal and a respective one of the multi-phasesignals at a predetermined transition of the other of the second digitalsignal and the respective multi-phase signal; and examining the firstoutput signals to determine the relative timing between first and seconddigital signals.
 30. The method of claim 29, further comprising:delaying the second digital signal to produce a plurality of seconddelayed signals that are delayed from the second digital signal byrespective second delay times; generating a plurality of second outputsignals each of which has a logic level corresponding to the logic levelof one of the first digital signal and a respective one of themulti-phase signals at a predetermined transition of the other of thefirst digital signal and the respective multi-phase signal; andexamining the second output signals along with the first output signalsto determine the relative timing between first and second digitalsignals. 31-35. (canceled)
 36. The system of claim 1, further comprisinga selector having an output terminal coupled to the multi-phase signalgenerator, the selector receiving a plurality of digital input signalsthat may have logic levels and phases that are different from eachother, the selector being operable to select one of the digital inputsignals and apply the selected digital input signal to the outputterminal as the first digital signal.
 37. The system of claim 1 whereinthe multi-phase signals generated by the phase mixers have respectivedelay times that differ from each other by the same delay interval. 38.The system of claim 4, further comprising a selector having an outputterminal coupled to the second multi-phase signal generator, theselector receiving a plurality of digital input signals that may havelogic levels and phases that are different from each other, the selectorbeing operable to select one of the digital input signals and apply theselected digital input signal to the output terminal as the seconddigital signal.
 39. A system for determining the relative timing betweenfirst and second digital signals, comprising: a multi-phase signalgenerator receiving the first digital signal, the multi-phase signalgenerator being operable to generate a plurality of multi-phase signalsthat are delayed from the first digital signal by respective percentagesof a first delay time; and a plurality of phase detectors each of whichis coupled to receive the second digital signal and a respective one ofthe multi-phase signals from the multi-phase signal generator, each ofthe phase detectors being structured to generate an output signal havinga logic level corresponding to the logic level of one of the seconddigital signal and the respective multi-phase signal at a predeterminedtransition of the other of the second digital signal and the respectivemulti-phase signal.
 40. The system of claim 39, further comprising: asecond multi-phase signal generator receiving the second digital signal,the second multi-phase signal generator being operable to generaterespective second multi-phase signals that are delayed by respectivepercentages of a second delay time; and a plurality of second phasedetectors each of which is coupled to receive the first digital signaland a respective one of the second multi-phase signals from the secondmulti-phase signal generator, each of the second phase detectors beingstructured to generate an output signal having a logic levelcorresponding to the logic level of one of the first digital signal andthe respective second multi-phase signal at a predetermined transitionof the other of the first digital signal and the respective secondmulti-phase signal.
 41. The system of claim 39, further comprising aplurality of latches coupled to receive respective output signals fromthe phase detectors, the latches being operable to store the receivedoutput signals.
 42. The system of claim 39, further comprising aselector having an output terminal coupled to the multi-phase signalgenerator, the selector receiving a plurality of digital input signalsthat may have logic levels and phases that are different from eachother, the selector being operable to select one of the digital inputsignals and apply the selected digital input signal to the outputterminal as the first digital signal.
 43. A system for determining therelative timing between first and second digital signals, comprising: amulti-phase signal generator receiving the first digital signal, themulti-phase signal generator being operable to generate from the firstdigital signal a plurality of multi-phase signals that are delayed fromthe first digital signal by respective first delay times; and aplurality of phase detectors each of which is coupled to receive thesecond digital signal and a respective one of the multi-phase signalsfrom the multi-phase signal generator, each of the phase detectors beingstructured to generate an output signal having a logic levelcorresponding to the logic level of one of the second digital and therespective multi-phase signal at a predetermined transition of the otherof the second digital and the respective multi-phase signal.
 44. Thesystem of claim 43, further comprising: a second multi-phase signalgenerator receiving the second digital signal, the second multi-phasesignal generator being operable to generate from the second digitalsignal respective second multi-phase signals that are delayed from thesecond digital by respective second delay times; and a plurality ofsecond phase detectors each of which is coupled to receive the firstdigital signal and a respective one of the second multi-phase signalsfrom the second multi-phase signal generator, each of the second phasedetectors being structured to generate an output signal having a logiclevel corresponding to the logic level of one of the second digitalsignal and the respective second multi-phase signal at a predeterminedtransition of one of the second digital signal and the respective secondmulti-phase signal.
 45. The system of claim 43, further comprising aplurality of latches coupled to receive respective output signals fromthe phase detectors, the latches being operable to store the receivedoutput signals.
 46. The system of claim 43, further comprising aselector having an output terminal coupled to the multi-phase signalgenerator, the selector receiving a plurality of digital input signalsthat may have logic levels and phases that are different from eachother, the selector being operable to select one of the digital inputsignals and apply the selected digital input signal to the outputterminal as the first digital signal.
 47. A method of determining therelative timing between first and second digital signals, comprising:providing a plurality of first delayed signals, the first delayedsignals being delayed from each other by respective first delay times;generating a plurality of first output signals each of which has a logiclevel corresponding to the logic level of one of the second digitalsignal and a respective one of the first delayed signals at apredetermined transition of the other of the second digital signal andthe respective first delayed signal; and examining the first outputsignals to determine the relative timing between first and seconddigital signals.
 48. The method of claim 47, further comprising:providing a plurality of second delayed signals that are delayed fromthe second digital signal by respective second delay times; generating aplurality of second output signals each of which has a logic levelcorresponding to the logic level of one of the first digital signal anda respective one of the multi-phase signals at a predeterminedtransition of the other of the first digital signal and the respectivemulti-phase signal; and examining the second output signals along withthe first output signals to determine the relative timing between firstand second digital signals.
 49. The method of claim 47, furthercomprising storing the first output signals prior to the step ofexamining the first output signals.
 50. The method of claim 47 whereinthe respective first delay times are equal to each other.